The present invention concerns the design and manufacture of very large scale integrated (VLSI) circuits and pertains particularly to improved routing between logic blocks of integrated circuits.
When designing integrated circuits, logic blocks are located on the integrated circuit. Area between the logic blocks is utilized as routing channels. Within the routing channels are placed conductive lines which carry a power signal, a ground signal, a clock signal and various data signals. These signals are routed to the logic blocks.
A routing channel typically has several metal layers. The top layers, furthest from the substrate, are the most conductive and are generally utilized to distribute the power signal and the ground signal. The lower layers, closer to the substrate, are generally used to route data signals. These lower layers are less conductive than the top layers.
One problem with the typical assignment of routing layers is that some critical signals may not meet the target frequency of a design. One way to handle this is to "promote" these critical signals to run in the top layer. This solution, however, has several disadvantages. For example, because the top layer is generally reserved for the power signal and the ground signal, running a critical signal in the top layer is an exception to the general rule of reserving the top layer for the power signal and the ground signal. Implementing this exception can add to the cost of implementation. Also, care must be taken to prevent a critical signal promoted to the top layer from being located immediately above a signal on a lower layer, as this may cause excessive coupling noise, also known as crosstalk.